Within the semiconductor industry, the overall scaling trend has been to increase the silicon power density by increasing transistor density and operating frequency on processor devices. However, the power reductions gained from design and process modifications are not sufficient to offset the higher operating temperatures accompanying the increased power density. In turn, the semiconductor's electrical performance and reliability is significantly degraded at higher operating temperature, reducing the semiconductor's processor speed and lifespan. As such, it is increasingly important to lower the semiconductor junction temperatures across the structure, particularly avoiding local hot spots in areas that run at higher power density.
Currently, the majority of high performance processor devices are fabricated on a thin (about 2-4 μm), lightly-doped (about 1×1015-1×1016 carriers/cm3) epitaxial silicon layer grown over a heavily-doped (about 1019 carriers/cm3) silicon substrate wafer, wherein boron is a preferred dopant. This type of wafer is generally referred to as a P/P++ epitaxial wafer or P/P+ epitaxial wafer. Epitaxial silicon layers such as these are typically grown by a chemical vapor deposition process wherein a substrate is heated while a gaseous silicon compound is passed over the wafer surface to affect pyrolysis or decomposition.
The heavily-doped silicon substrate below the device layer is intended to provide protection against many common device failure mechanisms, such as device latch-up failures, failures related to diffusion leakage current, or some radiation event-related failures. For example, latch-up failure refers to an electron-collection phenomenon resulting in a dead short circuit at a parasitic junction, but which can be prevented using, inter alia, strategic doping designs. Therefore, the arrangement of a lightly-doped device layer on a heavily-doped silicon substrate provides desirable latch-up and low diffusion current characteristics.
One disadvantage to using a heavily-doped silicon substrate is its poor thermal conductivity, as compared to the lightly-doped device layer; the thermal conductivity of lightly-doped silicon has been reported to be about 20% greater than heavily-doped silicon, and possibly even higher. See, e.g., P. Komarov et al., Transient Thermo-Reflectance Measurements of the Thermal Conductivity and Interface Resistance of Metallized Natural and Isotopically-Pure Silicon, 34 Microelectronics Journal No. 12, at 1115-1118 (2003). The difference in thermal conductivity is significant because the majority of heat generated in the thin device layer is transferred to the ambient environment by dissipation through the silicon substrate, and lesser thermal conductivity tends to reduce efficiency and reliability.
To improve heat removal from the device layer, efforts have previously focused on improving the thermal transfer characteristics from the back of the silicon substrate, through the packaging, and to the environment during use. While design of the packaging material and heat sinks have reduced the thermal resistance at this interface to maintain lower die temperatures, such efforts do not address the problem of localized heating at hot spots in the device layer.
Backside autodoping, i.e., the migration of dopant atoms from the back or sides of the substrate into the device layer, is another problem commonly encountered when a heavily doped substrate is integrated with a lightly doped device layer. One conventional approach to limit this effect is to form a backside oxide seal on the highly doped substrate. However, the oxide seal can not be integrated into the epitaxial silicon structure in the case of double-side polished wafers.
Heavily doped substrates having a lightly doped epitaxial layer also present challenges when used in CMOS Image Sensor applications wherein backside illumination technology is desirable. Currently, commercially available image sensors are illuminated from the device side. For typical device-side illumination applications, a CMOS Image Sensor silicon wafer comprises a substrate that is doped to a P+ or P++ concentration and an epitaxial layer doped to a P concentration. The known use of device-side illumination cannot meet the scaling trends and goals in such applications, which include reducing pixel size and increasing circuit functionality via advanced metal interconnections. Backside illumination is believed to realize these goals, while also improving the device's fill factor and quantum efficiency. These terms are used as different ways to measure the net amount of light energy that is actually able to illuminate the image sensors. Fill factor, which refers to the percentage or fraction of the image sensor that is capable of being exposed to light, is reduced in traditional device-side illumination devices by increasingly complex metallization layers and films, as well as advanced device topography. As the fill factor decreases, so does the quantum efficiency, which measures how efficiency projected light is able to generate active electron carriers.
These desired improvements in image sensor performance are possible using backside illumination technology because device-side features such as device patterns, metallization layers, interconnects, and films do not impede the illumination process. The result is nearly 100% fill factor, improved flexibility in antireflection coatings, and increased quantum efficiency. Moreover, backside illumination allows for integration of advanced device architecture and interconnections. However, backside illumination must be performed within a few microns of the device side photodiode to efficiently convert visible light to electrical signals. This requires consistent and uniform material removal from the backside of the original, as-formed silicon structure to create a smooth backside surface, which requires thinning the silicon structure from several hundred microns to just a few microns, such as less than about 15 μm. Furthermore, the backside surface must be capable of being passivated against recombination of photon-generated carriers at the surface, while also directing these photon-generated carriers to a collecting photodiode with an electric field within the Image Sensor device. Such features are not readily ascertained using conventional mechanical or chemical means to thin the silicon structure. Mechanical means of thinning may not be feasible with such small dimensions, while controlling chemical removal rates is difficult within the tolerances of the image sensor's physical features.